I’m a Computer Engineering student at Purdue University (graduating December 2025). My work spans ASIC and FPGA design, AI hardware accelerators, and fintech systems. I’ve designed RISC-V FPUs, USB SoC modules, and convolution controllers for tensor cores.
Professionally, I’ve been a Product Owner Intern at CIMB, collaborating with designers and developers on mobile banking features, I serve as a UTA for Python for Data Science, and I work for the Krenicki Center for Business Analytics and Machine Learning at Purdue as Undergraduate Student Researcher – Machine Learning and Predictive Models. My career goal is to build ultra-low latency hardware for financial trading systems.
Outside of engineering, I enjoy traveling, discovering new food, and exploring national parks.
View ResumeDeveloped the Tensor Compute Accelerator (TCA) featuring both GEMM and convolution controllers. Integrated with a weight-stationary systolic array and 32-bank scratchpad memory, implementing im2col-based convolution and optimized data flow for high efficiency. Designed, simulated, and verified modules with RTL, testbenches, and performance evaluation.
Designed and implemented a single-precision IEEE-754 FPU for RISC-V, including adder, subtractor, and multiplier modules. Contributed to SystemVerilog RTL design, testbench development, and verification using QuestaSim to ensure correctness, precision, and performance.
Developed a reaction-time Whack-A-Mole game using an STM32F091 microcontroller, 32 x 32 LED matrix, and keypad. Implemented multiple difficulty levels, scoring system, and persistent high-score storage using I2C EEPROM. Designed modular firmware in C to control game logic, display, and input handling.
Designed and implemented a multicore RISC-V processor with caches to run single- and dual-threaded programs. Built incrementally from single-cycle and pipelined designs, adding cache hierarchy, shared memory bus, and thread-level parallelism. Evaluated throughput, instruction latency, and FPGA resource utilization, demonstrating improved scalability and performance.
Designed and tested a USB Full-Speed Bulk-Transfer Endpoint as an AHB-Lite SoC module. Implemented 16-entry, 16-bit data-width circular buffers for OUT/IN transactions with full/empty flags and read/write enable logic. Developed a testbench to simulate token transactions and verify data correctness, ensuring reliable USB protocol handling.
Researched and developed an AI-driven NPC simulation in Unreal Engine. Designed NPCs capable of recognizing and interacting with everyday objects through the Smart Objects framework, creating realistic, context-aware behaviors. Built high-fidelity simulations of the Purdue University campus to support architectural safety and accessibility research. Findings on sensory stimuli in gaming platforms were presented at the Spring Undergraduate Research Conference 2024.
Open to internships or full-time roles in ASIC Design, Digital Design, or Data Science. Always happy to connect and discuss projects!
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